Chip scale package structure and method of forming the same

ABSTRACT

A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation-In-Part of application Ser. No.16/430,076 filed on Jun. 3, 2019, which claims the benefit of U.S.Provisional Application No. 62/731,128 filed on Sep. 14, 2018, theentirety of which is incorporated by reference herein. This applicationalso claims the benefit of U.S. Provisional Application No. 62/881,434filed on Aug. 1, 2019, the entirety of which is incorporated byreference herein. This application also claims the benefit of U.S.Provisional Application No. 62/881,441 filed on Aug. 1, 2019, theentirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to semiconductor package technology, andin particular to a wafer level chip scale package (WLCSP) structure.

Description of the Related Art

Integrated circuit (IC) devices are fabricated in a semiconductor waferand divided into individual chips. Afterwards, those chips are assembledin package form to be used in electronic products. The package providesa structure to support the chip and protect the chip from theenvironment. The package also provides electrical connections to andfrom the chip.

In recent years, as electronic products have become increasinglymultifunctional and have been scaled down in size, there is a desire formanufacturers of semiconductor devices to make more devices formed on asingle semiconductor wafer, so that the electronic products that includethese devices can be made more compact. This results in many newchallenges to the structural and electrical design of the package.

Accordingly, a chip scale package (CSP) technology has been developed tosatisfy the industry's demands (e.g., the smaller chip size and formfactor). Moreover, a wafer level package (WLP) technology has also beenintroduced for the cost-effective fabrication of packages. Such atechnology is referred to as wafer-level chip scale package (WLCSP).

However, in the use of the WLCSP process, the surface of each chip inthe respective package is exposed to the environment after the packagesare separated from the package wafer. As a result, damage to the chipmay occur, thereby reducing the reliability of the semiconductorpackages. Thus, a novel semiconductor package structure and afabrication method thereof are desirable.

BRIEF SUMMARY OF THE INVENTION

Semiconductor package structures are provided. An exemplary embodimentof a semiconductor package structure includes a semiconductor die, aredistribution layer (RDL) structure, a protective insulating layer, anda conductive structure. The semiconductor die has a first surface, asecond surface opposite the first surface, and a third surface adjoinedbetween the first surface and the second surface. The RDL structure ison the first surface of the semiconductor die and is electricallycoupled to the semiconductor die. The protective insulating layer coversthe RDL structure, the second surface and the third surface of thesemiconductor die. The conductive structure passes through theprotective insulating layer and is electrically coupled to the RDLstructure.

Another exemplary embodiment of a semiconductor package structureincludes a semiconductor die, a first protective insulating layer, afirst redistribution layer (RDL) structure, a first passivation layer,and a plurality of conductive structures. The semiconductor die has afirst surface, a second surface opposite the first surface, and a thirdsurface adjoined between the first surface and the second surface. Thefirst protective insulating layer covers the first surface and the thirdsurface of the semiconductor die. The first RDL structure is over thefirst surface of the semiconductor die and is electrically coupled tothe semiconductor die and extends to directly above the first protectiveinsulating layer. The first passivation layer covers the firstprotective insulating layer and the first RDL structure. The pluralityof conductive structures passes through the first passivation layer andis electrically coupled to the first RDL structure.

Yet another exemplary embodiment of a semiconductor package structureincludes a semiconductor die, a first redistribution layer (RDL)structure, a first protective insulating layer, a first passivationlayer, a second RDL structure, a second passivation layer, and aplurality of conductive structures. The semiconductor die has a firstsurface, a second surface opposite the first surface, and a thirdsurface adjoined between the first surface and the second surface. Thefirst RDL structure is on the first surface of the semiconductor die andis electrically coupled to the semiconductor die. The first protectiveinsulating layer covers the first surface and the third surface of thesemiconductor die and surrounds the first RDL structure. The firstpassivation layer covers the first protective insulating layer and thefirst RDL structure. The second RDL structure is electrically coupled tothe semiconductor die through the first RDL structure, wherein thesecond RDL structure extends from the first RDL structure to above thefirst protective insulating layer. The second passivation layer coversthe second RDL structure. The plurality of conductive structures passesthrough the second passivation layer and is electrically coupled to thesecond RDL structure.

A detailed description is given in the following embodiments withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thesubsequent detailed description and examples with references made to theaccompanying drawings, wherein:

FIGS. 1A to 1F are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments.

FIG. 2A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 2B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 3A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 3B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIGS. 4A to 4E are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments.

FIG. 5A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 5B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIGS. 6A to 6E are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments.

FIG. 7A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 7B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 8A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 8B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 9A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 9B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIGS. 10A to 10E are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments.

FIG. 10F is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 11A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 11B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 12A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 12B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 13A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

FIG. 13B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is determined byreference to the appended claims.

The present invention will be described with respect to particularembodiments and with reference to certain drawings, but the invention isnot limited thereto and is only limited by the claims. The drawingsdescribed are only schematic and are non-limiting. In the drawings, thesize of some of the elements may be exaggerated for illustrativepurposes and not drawn to scale. The dimensions and the relativedimensions do not correspond to actual dimensions in the practice of theinvention.

FIGS. 1A to 1F are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments of the disclosure. As shown in FIG. 1A, a substrate 100 isprovided. In some embodiments, the substrate 100 may include a pluralityof chip regions and a scribe line region that surrounds the plurality ofchip regions and separates the adjacent chip regions from each other. Tosimplify the diagram, only two complete and adjacent chip regions C anda scribe line region S separating these chip regions C are depictedherein. The substrate 100 may be a silicon wafer so as to facilitate thewafer-level packaging process. For example, the substrate 100 may be asilicon substrate or another semiconductor substrate.

In some embodiments, the chip regions C of the substrate 100 includeintegrated circuits (not shown) therein. In some embodiments, aninsulating layer 104 is formed on the substrate 100. The insulatinglayer 104 may serve as an inter-dielectric (ILD) layer, an inter-metaldielectric (IMD) layer, a passivation layer or a combination thereof. Tosimplify the diagram, only a flat layer is depicted herein. In someembodiments, the insulating layer 104 is made of an inorganic material,such as silicon oxide (SiO_(x)), silicon nitride (SiN_(x)), siliconoxynitride (SiON), or a combination thereof, or another suitableinsulating material.

Moreover, the insulating layer 104 includes one or more conductive pads102 therein. The conductive pads 102 correspond to the chip regions C ofthe substrate 100 and are adjacent to the upper surface of the substrate100. The conductive pad 102 may be formed of metal, such as copper,aluminum, or another suitable metal material. To simplify the diagram,only one conductive pad 102 formed on the substrate 100 in each chipregion C and exposed from the insulating layer 104 is depicted herein asan example. In some embodiments, the ICs in the chip region C iselectrically connected to the corresponding conductive pad 102. Theaforementioned structure define a number of semiconductor dies/chipsafter the chip regions C are separated from each other by dicing thescribe line region S of the substrate 100.

In some embodiments, a conductive layer (not shown), such as a metallayer, is formed on the insulating layer 104 and passing through theinsulating layer 104 to electrically couple to the exposed pads 102 inthe chip regions C. Afterwards, the conductive layer is patterned toform a redistribution layer (RDL) structure 106 in each of the chipregions C, so that the RDL structure 106 is electrically coupled to thesubsequent formed semiconductor die, as shown in FIG. 1A.

As shown in FIG. 1B, in some embodiments, the chip regions C areseparated from each other by dicing the scribe line region S of thesubstrate 100 to form semiconductor dies with the RDL structures 106thereon. The formed semiconductor die may be a system on chip (SOC)integrated circuit die. The SOC integrated circuit die, for example, mayinclude a logic die including a central processing unit (CPU), agraphics processing unit (GPU), a dynamic random access memory (DRAM)controller or any combination thereof. Each of semiconductor diesincludes a substrate 100, at least one conductive pad 102 formed on thesubstrate 100, and an insulating layer 104 formed over the substrate 100and having an opening to expose the conductive pad 102. Moreover, thesemiconductor die has a first surface 101 a (e.g., an active surface ofthe semiconductor die), a second surface 101 b (e.g., a non-activesurface of the semiconductor die) opposite the first surface 101 a, anda third surface 101 c (e.g., a sidewall surface of the semiconductordie) adjoined between the first surface 101 a and the second surface 101b.

As shown in FIG. 1B, in some embodiments, a carrier substrate 200 withan adhesive layer 202 formed thereon is provided. The carrier substrate200 may be made of silicon, glass, ceramic or the like, and may have ashape that is the same or similar to the semiconductor wafer, andtherefore the carrier substrate 200 is sometimes referred to as acarrier wafer. The adhesive layer 202 may be made of a light-to-heatconversion (LTHC) material or another suitable material. Afterwards, insome embodiments, the second surface 101 b of each semiconductor diethat has an RDL structure 106 formed on the first surface 101 a of thesemiconductor die is mounted onto the carrier substrate 200 via theadhesive layer 202 using a pick-and-place process.

Next, in some embodiments, a protective insulating layer 110 is formedto cover the first surface 101 a and the third surface 101 c of thesemiconductor dies and to surround the RDL structures 106, so that eachof the formed semiconductor dies with an RDL structure 106 thereon isencapsulated by the protective insulating layer 110. In someembodiments, the protective insulating layer 110 protects thesemiconductor dies from the environment, thereby preventing thesemiconductor die in the subsequently formed semiconductor packagestructure from damage due to, for example, the stress, the chemicalsand/or the moisture.

In some embodiments, the protective insulating layer 110 is made of anepoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or anacrylic-based material. In some embodiments, the protective insulatinglayer 110 is made of an epoxy molding compound (EMC) and formed by amolding process. For example, the protective insulating layer 110 (suchas in an epoxy or resin) may be applied while substantially liquid, andthen may be cured through a chemical reaction. The protective insulatinglayer 110 may be an ultraviolet (UV) or thermally cured polymer appliedas a gel or malleable solid capable of being formed around thesemiconductor dies, and then may be cured through a UV or thermal curingprocess. The protective insulating layer 110 may be cured with a mold(not shown).

After the protective insulating layer 110 is formed, the semiconductordies with RDL structures 106 encapsulated by the protective insulatinglayer 110 are de-bonded from the carrier substrate 200, as shown in FIG.1C. In some embodiments, a de-bonding process is performed by exposingthe adhesive layer 202 (shown in FIG. 1B) using a laser or UV light whenthe adhesive layer 202 is made of an LTHC material. The LTHC materialmay be decomposed due to generated heat from the laser or UV light, andhence the carrier substrate 200 is removed from the structure includingthe semiconductor dies, the RDL structures 106, and the protectiveinsulating layer 110. As a result, the second surface 101 b of eachsemiconductor die is exposed from the protective insulating layer 110.The resulting structure is shown in FIG. 1C.

In some embodiments, after the carrier substrate 200 is removed by thede-bonding process, a grinding process is performed on the top surfaceof the protective insulating layer 110 until the RDL structures 106 areexposed from the protective insulating layer 110, as shown in FIG. 1D.For example, the top surface of the protective insulating layer 110 maybe grinded by a chemical mechanical polishing (CMP) process or anothersuitable grinding process.

Afterwards, the protective insulating layer 110 and the RDL structures106 are covered with a passivation layer 112, as shown in FIG. 1E. Insome embodiments, the passivation layer 112 is formed on the protectiveinsulating layer 110 and the RDL structures 106 by a coating process oranother suitable deposition process. Afterwards, the passivation layer112 is patterned by lithography or a combination of lithograph andetching to form openings that expose the RDL structures 106. In someembodiments, the passivation layer 112 is made of a material that isdifferent from the material of the protective insulating layer 110. Insome embodiments, the passivation layer 112 is made of polyimide orpolybenzoxazole (PBO).

In some embodiments, during patterning the passivation layer 112, thepassivation layer 112 is also divided into several portions, so thateach of the semiconductor dies is covered by a respective portion ofpassivation layer 112. In some other embodiments, the passivation layer112 is divided into several portions by the subsequent dicing process.

After openings are formed in the passivation layer 112, conductivestructures 120 respectively pass through the passivation layer 112 viathose openings formed in the passivation layer 112, as shown in FIG. 1E.In some embodiments, the conductive structures 120 fill into theopenings formed in the passivation layer 112, so that each of theconductive structures 120 is electrically coupled to the respectiveexposed RDL structure 106 under the opening in the passivation layer112.

In some embodiments, the conductive structure 120 includes an optionalunder-bump metallurgy (UBM) layer 122 and a solder bump 124 on the UBMlayer 122. In some other embodiments, the conductive structure 120includes a conductive bump structure such as a copper bump, a conductivepillar structure, a conductive wire structure, or a conductive pastestructure.

After the conductive structures 120 are formed, an optional protectiveinsulating layer 130 is formed to cover the exposed second surfaces 101b of the semiconductor dies, as shown in FIG. 1F. The protectiveinsulating layer 130 is sometimes referred to as a die backside film(DBF) that is made of a thermoset material, such as an epoxy resinmaterial. In some other embodiments, the protective insulating layer 130is made of a material that is the same as the material of the protectiveinsulating layer 110. For example, the protective insulating layer 130is made of an epoxy molding compound (EMC), an Ajinomoto™ Build-up Film(ABF), or an acrylic-based material.

In some embodiments, after the protective insulating layer 130 isformed, a singulation is carried out to saw through the formed structureshown in FIG. 1F. For example, a dicing process may be performed on theformed structure shown in FIG. 1F. As a result, multiple separatesemiconductor package structures are formed.

FIG. 2A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. In FIG. 2A, one of thesemiconductor package structures 10 a that is formed by dicing theformed structure shown in FIG. 1F is shown. Descriptions of elements ofthe embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIGS. 1A to 1F may be omitted forbrevity. In some embodiments, the semiconductor package structure 10 aincludes a semiconductor die that includes a substrate 100, at least oneconductive pad 102 formed on the substrate 100, and an insulating layer104 formed over the substrate 100 and having an opening to expose theconductive pad 102, as shown in FIG. 2A. The semiconductor die has afirst surface 101 a (e.g., an active surface of the semiconductor die),a second surface 101 b (e.g., a non-active surface of the semiconductordie) opposite the first surface 101 a, and a third surface 101 c (e.g.,a sidewall surface of the semiconductor die) adjoined between the firstsurface 101 a and the second surface 101 b.

In some embodiments, the semiconductor package structure 10 a furtherincludes a protective insulating layer 110 that covers the first surface101 a and the third surface 101 c of the semiconductor die, and aprotective insulating layer 130 that covers the second surface 101 b ofthe semiconductor die. The thickness of the portion of the protectiveinsulating layer 110 covering the first surface 101 a and the thicknessof the of the portion of the protective insulating layer 110 coveringthe third surface 101 c of the semiconductor die can be adjusted, so asto fine-tune the protection ability of the semiconductor packagestructure 10 a.

In some embodiments, the protective insulating layer 110 and theprotective insulating layer 130 are made of the same material ordifferent materials. For example, such a material may include an epoxymolding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or anacrylic-based material. Alternatively, the protective insulating layer110 is made of an epoxy molding compound (EMC), an Ajinomoto™ Build-upFilm (ABF), or an acrylic-based material, and the protective insulatinglayer 130 is made of a DBF material that includes a thermoset material,such as an epoxy resin material.

In some embodiments, the semiconductor package structure 10 a furtherincludes an RDL structure 106 electrically coupled to the semiconductordie via the conductive pad 102 and surrounded by the protectiveinsulating layer 110 on the first surface 101 a of the semiconductordie.

In some embodiments, the semiconductor package structure 10 a furtherincludes a passivation layer 112 covering the RDL structure 106 and aportion of the protective insulating layer 110 surrounding the RDLstructure 106. The passivation layer 112 may be made of polyimide orpolybenzoxazole (PBO).

In some embodiments, the semiconductor package structure 10 a furtherincludes at least one conductive structure 120 that includes an optionalUBM layer 122 and a solder bump 124 and passes through the passivationlayer 112, so as to be electrically coupled to the semiconductor diethrough the RDL structure 106.

In some embodiments, the semiconductor package structure 10 a shown inFIG. 2A is a CSP structure. The CSP structure may include an SOCpackage. Moreover, the semiconductor package structure 10 a may bemounted on a base (not shown). The base may include a printed circuitboard (PCB) and may be formed of polypropylene (PP). Alternatively, thebase may include a package substrate. The semiconductor packagestructure 10 a may be mounted on the base by a bonding process. Forexample, the semiconductor package structure 10 a may be mounted on thebase by the bonding process and electrically coupled to the base usingthe conductive structures 120 as connectors.

FIG. 2B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 2A may be omitted forbrevity. In some embodiments, the semiconductor package structure 10 bis similar to the semiconductor package structure 10 a shown in FIG. 2A.Compared to the semiconductor package structure 10 a, there is noprotective insulating layer 130 formed in the package structure 10 b,and hence the second surface 101 b of the semiconductor die is exposedto the environment. In some embodiments, the semiconductor packagestructure 10 b is formed by a method that is similar to the method shownin FIGS. 1A to 1F, except that the formation of the protectiveinsulating layer 130, as shown in FIG. 1F, is omitted. Namely, after thestructure shown in FIG. 1E is formed, a singulation is carried out tosaw through the formed structure shown in FIG. 1E.

FIG. 3A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 2A may be omitted forbrevity. In some embodiments, the semiconductor package structure 10 cis similar to the semiconductor package structure 10 a shown in FIG. 2A.Compared to the semiconductor package structure 10 a, the semiconductorpackage structure 10 c further includes a passivation layer 105 formedbetween the first surface 101 a of the semiconductor die and the RDLstructure 106 and covered by the protective insulating layer 110. Insome embodiments, the material and the method used for the passivationlayer 105 are the same as or similar to those used for the passivationlayer 112. For example, the passivation layer 105 is made of polyimideor polybenzoxazole (PBO). In some embodiments, the semiconductor packagestructure 10 c is formed by a method that is similar to the method shownin FIGS. 1A to 1F, except that an additional passivation layer 105 isformed prior to the formation of the RDL structure 106. Prior to theformation of the RDL structure 106, at least one opening is formed inthe passivation layer 105, so that the passivation layer 105 exposes theconductive pad 102 and surrounds the opening formed in the insulatinglayer 104.

FIG. 3B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIGS. 2A and 3A may be omittedfor brevity. In some embodiments, the semiconductor package structure 10d is similar to the semiconductor package structure 10 c shown in FIG.3A. Compared to the semiconductor package structure 10 c, there is noprotective insulating layer 130 formed in the package structure 10 d,and hence the second surface 101 b of the semiconductor die is exposedto the environment. In some embodiments, the semiconductor packagestructure 10 d is formed by a method that is similar to the method usedfor forming the semiconductor package structure 10 c, except that theformation of the protective insulating layer 130 is omitted.

FIGS. 4A to 4E are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments of the disclosure. Descriptions of elements of theembodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIGS. 1A to 1F may be omitted forbrevity. As shown in FIG. 4A, a structure as shown in FIG. 1A isprovided. Afterwards, a protective insulating layer 110 a is formed tocover the first surface 101 a of each semiconductor die and surroundeach RDL structure 106, so that the top surfaces and sidewalls of theRDL structures 106 are covered or encapsulated by the protectiveinsulating layer 110 a. In some embodiments, the protective insulatinglayer 110 a is made of an epoxy molding compound (EMC), an Ajinomoto™Build-up Film (ABF), or an acrylic-based material. In some embodiments,the protective insulating layer 110 a is formed by a coating process, amolding process, or another suitable process.

As shown in FIG. 4B, in some embodiments, after the protectiveinsulating layer 110 a is formed, the chip regions C are separated fromeach other by dicing the scribe line region S of the substrate 100 toform semiconductor dies with the RDL structures 106 thereon. The formedsemiconductor die has a first surface 101 a (e.g., an active surface ofthe semiconductor die), a second surface 101 b (e.g., a non-activesurface of the semiconductor die) opposite the first surface 101 a, anda third surface 101 c (e.g., a sidewall surface of the semiconductordie) adjoined between the first surface 101 a and the second surface 101b. Moreover, the protective insulating layer 110 a has a sidewall 109that is substantially aligned with the third surface 101 c of thesemiconductor die.

Still referring to FIG. 4B, in some embodiments, a carrier substrate 200with an adhesive layer 202 formed thereon is provided. Afterwards, insome embodiments, each of the formed semiconductor dies with an RDLstructure 106 formed on the first surface 101a of the semiconductor dieis mounted onto the carrier substrate 200 by attaching the top surfaceof the protective insulating layer 110 a to the adhesive layer 202 usinga pick-and-place process. As a result, the second surface 101 b of eachsemiconductor die is opposite the carrier substrate 200.

Next, in some embodiments, a protective insulating layer 110 is formedusing a molding process to cover the second surface 101 b and the thirdsurface 101 c of the semiconductor dies and surround the protectiveinsulating layer 110 a, so that the protective insulating layer 110extends from the third surface 101 c of each semiconductor die to thesidewall 109 of the respective protective insulating layer. As a result,each of the formed semiconductor dies with an RDL structure 106 thereonis encapsulated by a protective structure including the protectiveinsulating layer 110 a and the protective insulating layer 110.

In some embodiments, the protective structure protects the semiconductordies from the environment, thereby preventing the semiconductor die inthe subsequently formed semiconductor package structure from damage dueto, for example, the stress, the chemicals and/or the moisture. In someembodiments, the protective insulating layer 110 of the protectivestructure is formed by a molding process while the protective insulatinglayer 110 a of the protective structure is formed by a coating process.

After the protective structure is formed, the semiconductor dies withRDL structures 106 encapsulated by the protective structure arede-bonded from the carrier substrate 200 by a de-bonding process asshown in FIG. 1C. The resulting structure is shown in FIG. 4C.

In some embodiments, after the carrier substrate 200 is removed by thede-bonding process, a grinding process is performed on the protectiveinsulating layer 110 a above the RDL structures 106 and a portion of theprotective insulating layer 110 surrounding the protective insulatinglayer 110 a until the RDL structures 106 are exposed from the protectiveinsulating layer 110 a, as shown in FIG. 4D. For example, the protectiveinsulating layer 110 a and the protective insulating layer 110 may begrinded by a CMP process or another suitable grinding process.

Afterwards, the protective insulating layer 110 a and the RDL structures106 are covered with a patterned passivation layer 112, as shown in FIG.4E. In some embodiments, the passivation layer 112 is made of a materialthat is different from the material of the protective insulating layer110 a and the material of the protective insulating layer 110. In someembodiments, during patterning the passivation layer 112, thepassivation layer 112 is also divided into several portions, so thateach of the semiconductor dies is covered by a respective portion ofpassivation layer 112. In some other embodiments, the passivation layer112 is divided into several portions by the subsequent dicing process.

After openings are formed in the passivation layer 112, conductivestructures 120 including an optional UBM layer 122 and a solder bump 124respectively pass through the passivation layer 112 via those openings,as shown in FIG. 4E. As a result, each of the conductive structures 120is electrically coupled to the respective exposed RDL structure 106.

In some embodiments, after the conductive structures 120 is formed, asingulation (e.g., a dicing process) is carried out to saw through theformed structure shown in FIG. 4E. As a result, multiple separatesemiconductor package structures are formed.

FIG. 5A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. In FIG. 5A, one of thesemiconductor package structures 20 a that is formed by dicing theformed structure shown in FIG. 4E is shown. Descriptions of elements ofthe embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIGS. 4A to 4E may be omitted forbrevity. In some embodiments, the semiconductor package structure 20 aincludes a semiconductor die that includes a substrate 100, at least oneconductive pad 102 formed on the substrate 100, and an insulating layer104 formed over the substrate 100 and having an opening to expose theconductive pad 102, as shown in FIG. 5A. The semiconductor die has afirst surface 101 a (e.g., an active surface of the semiconductor die),a second surface 101 b (e.g., a non-active surface of the semiconductordie) opposite the first surface 101 a, and a third surface 101 c (e.g.,a sidewall surface of the semiconductor die) adjoined between the firstsurface 101 a and the second surface 101 b.

In some embodiments, the semiconductor package structure 20 a furtherincludes a protective insulating layer 110 a that covers the firstsurface 101 a of the semiconductor die, and a protective insulatinglayer 110 that covers the second surface 101 b and the third surface 101c of the semiconductor die and that surrounds the protective insulatinglayer 110 a. The protective insulating layer 110 a has a sidewall 109that is substantially aligned with the third surface 101 c of thesemiconductor die. The protective insulating layer 110 extends from thethird surface 101 c of the semiconductor die to the sidewall 109 of theprotective insulating layer 110 a. The thickness of the protectiveinsulating layer 110 a covering the first surface 101 a and thethickness of the protective insulating layer 110 covering the secondsurface 101 b and the third surface 101 c of the semiconductor die canbe adjusted, so as to fine-tune the protection ability of thesemiconductor package structure 20 a.

In some embodiments, the protective insulating layer 110 a and theprotective insulating layer 110 are made of the same material ordifferent materials. For example, such a material may include an epoxymolding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or anacrylic-based material.

In some embodiments, the semiconductor package structure 20 a furtherincludes an RDL structure 106 electrically coupled to the semiconductordie via the conductive pad 102 and surrounded by the protectiveinsulating layer 110 a.

In some embodiments, the semiconductor package structure 20 a furtherincludes a passivation layer 112 covering the RDL structure 106 and aportion of the protective insulating layer 110 a surrounding the RDLstructure 106. Moreover, the passivation layer 112 is made of forexample, polyimide or polybenzoxazole (PBO).

In some embodiments, the semiconductor package structure 20 a furtherincludes at least one conductive structure 120 that includes an optionalUBM layer 122 and a solder bump 124 and passes through the passivationlayer 112, so as to be electrically coupled to the semiconductor diethrough the RDL structure 106.

In some embodiments, the semiconductor package structure 20 a shown inFIG. 5A is a CSP structure. The CSP structure may include an SOCpackage. Moreover, the semiconductor package structure 20 a may bemounted on a base (not shown). The base may include a printed circuitboard (PCB) and may be formed of polypropylene (PP). Alternatively, thebase may include a package substrate. Similar to the semiconductorpackage structure 10 a, the semiconductor package structure 20 a may bemounted on the base by a bonding process and electrically coupled to thebase using the conductive structures 120 as connectors.

FIG. 5B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 5A may be omitted forbrevity. In some embodiments, the semiconductor package structure 20 bis similar to the semiconductor package structure 20 a shown in FIG. 5A.Compared to the semiconductor package structure 20 a, the semiconductorpackage structure 20 b further includes a passivation layer 105 formedbetween the first surface 101 a of the semiconductor die and the RDLstructure 106 and covered by the protective insulating layer 110 a. Insome embodiments, the material and the method used for the passivationlayer 105 are the same as or similar to those used for the passivationlayer 112 and different from those used for the protective insulatinglayer 110 a and those used for the protective insulating layer 110. Insome embodiments, the semiconductor package structure 20 b is formed bya method that is similar to the method shown in FIGS. 4A to 4E, exceptthat an additional passivation layer 105 is formed prior to theformation of the RDL structure 106. Prior to the formation of the RDLstructure 106, at least one opening is formed in the passivation layer105, so that the passivation layer 105 exposes the conductive pad 102and surrounds the opening formed in the insulating layer 104.

FIGS. 6A to 6E are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments of the disclosure. Descriptions of elements of theembodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIGS. 1A to 1F or 4A to 4E may beomitted for brevity. As shown in FIG. 6A, a structure as shown in FIG.1A is provided. Afterwards, the chip regions C are separated from eachother by dicing the scribe line region S of the substrate 100 to formsemiconductor dies with the RDL structures 106 thereon. The formedsemiconductor die has a first surface 101 a (e.g., an active surface ofthe semiconductor die), a second surface 101 b (e.g., a non-activesurface of the semiconductor die) opposite the first surface 101 a, anda third surface 101 c (e.g., a sidewall surface of the semiconductordie) adjoined between the first surface 101 a and the second surface 101b.

As shown in FIG. 6A, in some embodiments, a carrier substrate 200 withan adhesive layer 202 formed thereon is provided. Afterwards, in someembodiments, each of the formed semiconductor dies with an RDL structure106 formed on the first surface 101 a of the semiconductor die ismounted onto the carrier substrate 200 by attaching the top surface andsidewall surface of the RDL structure 106 to the adhesive layer 202using a pick-and-place process. As a result, the second surface 101 b ofeach semiconductor die is opposite the carrier substrate 200.

Next, in some embodiments, a protective insulating layer 110 is formedusing a molding process to cover the second surface 101 b and the thirdsurface 101 c of the semiconductor dies and surround the protectiveinsulating layer 110 a, so that the protective insulating layer 110extends from the third surface 101 c of each semiconductor die to thesidewall 109 of the respective protective insulating layer.

In some embodiments, after the protective insulating layer 110 isformed, the semiconductor dies with RDL structures 106 are de-bondedfrom the carrier substrate 200 by a de-bonding process (as shown in FIG.1C). The resulting structure is shown in FIG. 6B.

In some embodiments, after the de-bonding process, a protectiveinsulating layer 110 a is formed by a coating process to cover the firstsurface 101 a of each semiconductor die and surround each RDL structure106, as shown in FIG. 6C. As a result, the top surfaces and sidewalls ofthe RDL structures 106 are covered or encapsulated by the protectiveinsulating layer 110 a. Moreover, a portion of the protective insulatinglayer 110 covering the third surface 101 c of the semiconductor die iscapped by the protective insulating layer 110 a. In some otherembodiments, the protective insulating layer 110 a is formed by amolding process or another suitable process.

Due to the formation of a protective structure including the protectiveinsulating layer 110 a and the protective insulating layer 110, each ofthe formed semiconductor dies with an RDL structure 106 thereon isencapsulated. The protective structure protects the semiconductor diesfrom the environment, thereby preventing the semiconductor die in thesubsequently formed semiconductor package structure from damage due to,for example, the stress, the chemicals and/or the moisture.

In some embodiments, after the protective structure is formed, agrinding process is performed on the protective insulating layer 110 aabove the RDL structures 106 until the RDL structures 106 are exposedfrom the protective insulating layer 110 a, as shown in FIG. 6D. Forexample, the protective insulating layer 110 a may be grinded by a CMPprocess or another suitable grinding process.

Afterwards, the protective insulating layer 110 a and the RDL structures106 are covered with a patterned passivation layer 112, as shown in FIG.6E. In some embodiments, the passivation layer 112 is made of a materialthat is different from the material of the protective insulating layer110 a and the material of the protective insulating layer 110. In someembodiments, during patterning the passivation layer 112, thepassivation layer 112 is also divided into several portions, so thateach of the semiconductor dies is covered by a respective portion ofpassivation layer 112. In some other embodiments, the passivation layer112 is divided into several portions by the subsequent dicing process.

After openings are formed in the passivation layer 112, conductivestructures 120 including an optional UBM layer 122 and a solder bump 124respectively pass through the passivation layer 112 via those openings,as shown in FIG. 6E. As a result, each of the conductive structures 120is electrically coupled to the respective exposed RDL structure 106.

In some embodiments, after the conductive structures 120 is formed, asingulation (e.g., a dicing process) is carried out to saw through theformed structure shown in FIG. 6E. As a result, multiple separatesemiconductor package structures are formed. In some embodiments, in thesemiconductor package structure, the protective insulating layer 110 ahas a sidewall and a portion of the protective insulating layer coveringthe third surface 101 c of the semiconductor die has a sidewall, andthose sidewalls are substantially aligned with each other.

FIG. 7A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. In FIG. 7A, one of thesemiconductor package structures 30 a that is formed by dicing theformed structure shown in FIG. 6E is shown. Descriptions of elements ofthe embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIGS. 1A to 1F or 4A to 4E may beomitted for brevity. In some embodiments, the semiconductor packagestructure 30 a includes a semiconductor die that includes a substrate100, at least one conductive pad 102 formed on the substrate 100, and aninsulating layer 104 formed over the substrate 100 and having an openingto expose the conductive pad 102, as shown in FIG. 7A. The semiconductordie has a first surface 101 a (e.g., an active surface of thesemiconductor die), a second surface 101 b (e.g., a non-active surfaceof the semiconductor die) opposite the first surface 101 a, and a thirdsurface 101 c (e.g., a sidewall surface of the semiconductor die)adjoined between the first surface 101 a and the second surface 101 b.

In some embodiments, the semiconductor package structure 30 a furtherincludes a protective insulating layer 110 a that covers the firstsurface 101 a of the semiconductor die, and a protective insulatinglayer 110 that covers the second surface 101 b and the third surface 101c of the semiconductor die and that surrounds the protective insulatinglayer 110 a. The protective insulating layer 110 a has a sidewall 109and a portion of the protective insulating layer 110 a covering thethird surface 101 c of the semiconductor die has a sidewall 113. In someembodiments, the sidewall 109 is substantially aligned with the sidewall113. Moreover, the portion of the protective insulating layer 110covering the third surface 101 c of the semiconductor die is capped bythe protective insulating layer 110 a. The thickness of the protectiveinsulating layer 110 a covering the first surface 101 a and thethickness of the protective insulating layer 110 covering the secondsurface 101 b and the third surface 101 c of the semiconductor die canbe adjusted, so as to fine-tune the protection ability of thesemiconductor package structure 30 a.

In some embodiments, the protective insulating layer 110 a and theprotective insulating layer 110 are made of the same material ordifferent materials. For example, such a material may include an epoxymolding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or anacrylic-based material.

In some embodiments, the semiconductor package structure 30 a furtherincludes an RDL structure 106 electrically coupled to the semiconductordie via the conductive pad 102 and surrounded by the protectiveinsulating layer 110 a.

In some embodiments, the semiconductor package structure 30 a furtherincludes a passivation layer 112 covering the RDL structure 106 and aportion of the protective insulating layer 110 a surrounding the RDLstructure 106. Moreover, the passivation layer 112 is made of forexample, polyimide or polybenzoxazole (PBO).

In some embodiments, the semiconductor package structure 30 a furtherincludes at least one conductive structure 120 that includes an optionalUBM layer 122 and a solder bump 124 and passes through the passivationlayer 112, so as to be electrically coupled to the semiconductor diethrough the RDL structure 106.

In some embodiments, the semiconductor package structure 30 a shown inFIG. 7A is a CSP structure. The CSP structure may include an SOCpackage. Moreover, the semiconductor package structure 30 a may bemounted on a base (not shown). The base may include a printed circuitboard (PCB) and may be formed of polypropylene (PP). Alternatively, thebase may include a package substrate. Similar to the semiconductorpackage structure 10 a or 20 a, the semiconductor package structure 30 amay be mounted on the base by a bonding process and electrically coupledto the base using the conductive structures 120 as connectors.

FIG. 7B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 7A may be omitted forbrevity. In some embodiments, the semiconductor package structure 30 bis similar to the semiconductor package structure 30 a shown in FIG. 7A.Compared to the semiconductor package structure 30 a, the semiconductorpackage structure 30 b further includes a passivation layer 105 formedbetween the first surface 101 a of the semiconductor die and the RDLstructure 106 and covered by the protective insulating layer 110 a. Insome embodiments, the material and the method used for the passivationlayer 105 are the same as or similar to those used for the passivationlayer 112 and different from those used for the protective insulatinglayer 110 a and those used for the protective insulating layer 110. Insome embodiments, the semiconductor package structure 30 b is formed bya method that is similar to the method shown in FIGS. 6A to 6E, exceptthat an additional passivation layer 105 is formed prior to theformation of the RDL structure 106. Prior to the formation of the RDLstructure 106, at least one opening is formed in the passivation layer105, so that the passivation layer 105 exposes the conductive pad 102and surrounds the opening formed in the insulating layer 104.

FIG. 8A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 7A may be omitted forbrevity. In some embodiments, the semiconductor package structure 40 ais similar to the semiconductor package structure 30 a shown in FIG. 7A.Compared to the semiconductor package structure 30 a, the passivationlayer 112 is formed on the RDL structure 106 and the protectiveinsulating layer 110 without forming the protective insulating layer 110a in the semiconductor package structure 40 a. In some embodiments, thesemiconductor package structure 40 a is formed by a method that issimilar to the method illustrated in FIG. 7A, except that the protectiveinsulating layer 110 a is not formed. The passivation layer 112 may beformed after the formation of the RDL structure 106. As shown in FIG.8A, the passivation layer 112 covers the sidewall of the RDL structure106.

FIG. 8B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 8A may be omitted forbrevity. In some embodiments, the semiconductor package structure 40 bis similar to the semiconductor package structure 40 a shown in FIG. 8A.Compared to the semiconductor package structure 40 a, the semiconductorpackage structure 40 b further includes a passivation layer 105 formedbetween the first surface 101 a of the semiconductor die and the RDLstructure 106 and covered by the passivation layer 112. In someembodiments, the material and the method used for the passivation layer105 are the same as or similar to those used for the passivation layer112 and different from those used for the protective insulating layer110. As shown in FIG. 8B, the passivation layer 112 covers the sidewallof the RDL structure 106 and the sidewall of the passivation layer 105.

In some embodiments, the semiconductor package structure 40 b is formedby a method that is similar to the method illustrated in FIG. 8A, exceptthat an additional passivation layer 105 is formed prior to theformation of the RDL structure 106. Prior to the formation of the RDLstructure 106, at least one opening is formed in the passivation layer105, so that the passivation layer 105 exposes the conductive pad 102and surrounds the opening formed in the insulating layer 104.

FIG. 9A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 8A may be omitted forbrevity. In some embodiments, the semiconductor package structure 50 ais similar to the semiconductor package structure 40 a shown in FIG. 8A.Compared to the semiconductor package structure 40 a, the protectiveinsulating layer 110 further covers the RDL structure 106 and thepassivation layer 112 in the semiconductor package structure 50 a.

In some embodiments, the semiconductor package structure 50 a is formedby a method that is similar to the method illustrated in FIG. 8A, exceptthat the protective insulating layer 110 is formed before the formationof the conductive structure 120 and after the formation of thepassivation layer 112. In some embodiments, after the formation of thepassivation layer 112, the protective insulating layer 110 is formed tocover the second surface 101 b and the third surface 101 c of thesemiconductor die, the RDL structure 106, and the passivation layer 112.In other words, the embodiments according to FIGS. 1A-8B may be referredto as recon first, and the embodiments according to FIG. 9A may bereferred to as recon last.

Next, at least one opening may be formed in the protective insulatinglayer 110 and passing through the passivation layer 112, so that thepassivation layer 112 and the protective insulating layer 110 expose theRDL structure 106. Next, the conductive structure 120 is formed in theopenings. In some embodiments, the conductive structure 120 includes anoptional UBM layer 122 and a solder bump 124 on the UBM layer 122. Insome other embodiments, the UBM layer 122 is not formed, and theconductive structure 120 includes a solder bump 124 on the passivationlayer 112.

Various steps may be added, removed, rearranged and repeated. Forexample, in the embodiment where the conductive structure 120 includingthe UBM layer 122 and the solder bump 124, the protective insulatinglayer 110 may be formed after the formation of the UBM layer 122 andbefore the formation of the solder bump 124. In these embodiments, afterthe protective insulating layer 110 is formed, a grinding process isperformed on the top surface of the protective insulating layer 110until the UBM layer 122 is exposed from the protective insulating layer110. For example, the top surface of the protective insulating layer 110may be grinded by a chemical mechanical polishing (CMP) process oranother suitable grinding process. Next, the solder bump 124 is formedon the exposed UBM layer 122.

In some embodiments, the edge of the passivation layer 112 is alignedwith the third surface 101 c of the semiconductor die as shown in FIG.9A, but the present disclosure is not limit thereto. For example, theedge of the passivation layer 112 may be disposed inside the firstsurface 101 a of the semiconductor die in some other embodiments. Inthese embodiments, a portion of the first surface 101 a of thesemiconductor die exposed by the passivation layer 112 is in contactwith the protective insulating layer 110.

In some embodiments, the RDL structure 106 is in contact with thepassivation layer 112 as shown in FIG. 9A, but the present disclosure isnot limit thereto. For example, the passivation layer 112 may not beformed, and the RDL structure 106 may be in contact with the protectiveinsulating layer 110 in some other embodiments. In these embodiments,the protective insulating layer 110 is formed after the formation of theRDL structure 106. Alternatively, a portion of the top surface of theRDL structure 106 may be in contact with the passivation layer 112, andanother portion of the top surface of the RDL structure 106 may be incontact with the protective insulating layer 110.

According to some embodiments, in addition to the second surface 101 band the third surface 101 c of the semiconductor die, the protectiveinsulating layer 110 further covers the RDL structure 106 and thepassivation layer 112 can provide an better protection ability of thesemiconductor package structure 50 a. Furthermore, the semiconductor dieshift for the RDL structure alignment can be reduced or avoided.Therefore, reliability of the semiconductor package structure 50 b canbe improved.

FIG. 9B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 9A may be omitted forbrevity. In some embodiments, the semiconductor package structure 50 bis similar to the semiconductor package structure 50 a shown in FIG. 9A.Compared to the semiconductor package structure 50 a, the semiconductorpackage structure 50 b further includes a passivation layer 105 formedbetween the first surface 101 a of the semiconductor die and the RDLstructure 106 and covered by the protective insulating layer 110. Insome embodiments, the material and the method used for the passivationlayer 105 are the same as or similar to those used for the passivationlayer 112 and different from those used for the protective insulatinglayer 110.

In some embodiments, the semiconductor package structure 50 b is formedby a method that is similar to the method described in FIG. 9A, exceptthat an additional passivation layer 105 is formed prior to theformation of the RDL structure 106. Prior to the formation of the RDLstructure 106, at least one opening is formed in the passivation layer105, so that the passivation layer 105 exposes the conductive pad 102and surrounds the opening formed in the insulating layer 104.

FIGS. 10A to 10E are cross-sectional views of an exemplary method offorming a semiconductor package structure in accordance with someembodiments of the disclosure. Descriptions of elements of theembodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIGS. 1A to 1F, 4A to 4E or 6A to6E may be omitted for brevity. Compared to the semiconductor packagestructure 10 a-50 b as shown in FIGS. 1A-9B, the following embodimentprovides a semiconductor package structure with a fan-out structure.

As shown in FIG. 10A, in some embodiments, a substrate 100 is provided.The substrate 100 may be a silicon wafer. For example, the substrate 100may be a silicon substrate or another semiconductor substrate. In someembodiments, the substrate 100 include integrated circuits (not shown)therein.

In some embodiments, an insulating layer 104 is formed on the substrate100. The insulating layer 104 may serve as an ILD layer, an IMD layer, apassivation layer or a combination thereof. To simplify the diagram,only a flat layer is depicted herein. In some embodiments, theinsulating layer 104 is made of an inorganic material, such as siliconoxide (SiO_(x)), silicon nitride (SiN_(x)), silicon oxynitride (SiON), acombination thereof, or another suitable insulating material.

Moreover, the insulating layer 104 includes one or more conductive pads102 therein. The conductive pads 102 are adjacent to the upper surfaceof the substrate 100. The conductive pad 102 may be formed of metal,such as copper, aluminum, or another suitable metal material. Twoconductive pads 102 formed on the substrate 100 and exposed from theinsulating layer 104 are depicted herein as an example, but the presentdisclosure is not limit thereto. For example, one or more than twoconductive pads 102 may be formed on the substrate 100.

In some embodiments, a conductive layer (not shown), such as a metallayer, is formed on the insulating layer 104 and passing through theinsulating layer 104 to electrically couple to the exposed conductivepads 102. Afterwards, the conductive layer is patterned to form a RDLstructure 106, so that the RDL structure 106 is electrically coupled tothe subsequent formed semiconductor die, as shown in FIG. 10A.

In some embodiments, the substrate 100 is diced to form semiconductordies with the RDL structure 106 thereon, as shown in FIG. 10A. Each ofthe formed semiconductor dies may be a SOC integrated circuit die. TheSOC integrated circuit die, for example, may include a logic dieincluding a CPU, a GPU, a DRAM controller, or any combination thereof.Each of the semiconductor dies includes a substrate 100, one or moreconductive pads 102 formed on the substrate 100, and an insulating layer104 formed over the substrate 100 and having an opening to expose theconductive pads 102. Moreover, the semiconductor die has a first surface101 a (e.g., an active surface of the semiconductor die), a secondsurface 101 b (e.g., a non-active surface of the semiconductor die)opposite the first surface 101 a, and a third surface 101 c (e.g., asidewall surface of the semiconductor die) adjoined between the firstsurface 101 a and the second surface 101 b.

In some embodiments, the second surface 101 b of each semiconductor diemay be mounted onto a carrier substrate (not shown) via an adhesivelayer (not shown) using a pick-and-place process. Next, in someembodiments, a protective insulating layer 110 is formed to cover thefirst surface 101 a and the third surface 101 c of the semiconductordies and to surround the RDL structure 106, so that each of the formedsemiconductor dies with an RDL structure 106 thereon is encapsulated bythe protective insulating layer 110. In some embodiments, the protectiveinsulating layer 110 protects the semiconductor dies from theenvironment, thereby preventing the semiconductor die in thesubsequently formed semiconductor package structure from damage due to,for example, the stress, the chemicals and/or the moisture.

In some embodiments, the protective insulating layer 110 is made of anepoxy molding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or anacrylic-based material. In some embodiments, the protective insulatinglayer 110 is made of an epoxy molding compound (EMC) and formed by amolding process. The exemplary formation of the protective insulatinglayer 110 is described above, and will not be repeated again.

After the protective insulating layer 110 is formed, the semiconductordie with the RDL structure 106 encapsulated by the protective insulatinglayer 110 is de-bonded from the carrier substrate. The exemplary methodof de-bonding is described above, and will not be repeated again. As aresult, the second surface 101 b of each semiconductor die is exposedfrom the protective insulating layer 110.

In some embodiments, after the carrier substrate is removed by thede-bonding process, a grinding process is performed on the top surfaceof the protective insulating layer 110 until the RDL structure 106 isexposed from the protective insulating layer 110, as shown in FIG. 10C.For example, the top surface of the protective insulating layer 110 maybe grinded by a CMP process or another suitable grinding process.

Afterwards, the protective insulating layer 110 and the RDL structure106 are covered with a passivation layer 112, as shown in FIG. 10D. Insome embodiments, the passivation layer 112 is formed on the protectiveinsulating layer 110 and the RDL structure 106 by a coating process oranother suitable deposition process. Afterwards, the passivation layer112 is patterned by lithography or a combination of lithograph andetching to form openings that expose the RDL structure 106. In someembodiments, the passivation layer 112 is made of a material that isdifferent from the material of the protective insulating layer 110. Insome embodiments, the passivation layer 112 is made of polyimide orpolybenzoxazole (PBO).

After openings are formed in the passivation layer 112, a RDL structure114 passes through the passivation layer 112 via those openings formedin the passivation layer 112, as shown in FIG. 10D. The formation andthe material of the RDL structure 114 may include the formation and thematerial as described above with respect to the RDL structure 106, andwill not be repeated again. In some embodiments, the RDL structure 114fills into the openings formed in the passivation layer 112, so thateach of the RDL structure 114 is electrically coupled to the respectiveexposed RDL structure 106 under the opening in the passivation layer112.

As shown in FIG. 10D, the RDL structure 114 extends from the RDLstructure 106 to above the protective insulating layer 110, according tosome embodiments. In particular, the RDL structure 114 may extend fromdirectly above the first surface 101 a of the semiconductor die todirectly above the protective insulating layer 110. Accordingly, the RDLstructure 114 enables the fan-out connection.

Afterwards, the protective insulating layer 110, the passivation layer112, and the RDL structure 114 are covered with a patterned passivationlayer 116, as shown in FIG. 10D. In some embodiments, the passivationlayer 116 is made of a material that is different from the material ofthe protective insulating layer 110. The formation and the material ofthe passivation layer 116 may include the formation and the material asdescribed above with respect to the passivation layer 112 or thepassivation layer 105, and will not be repeated again. Afterwards, thepassivation layer 116 is patterned by lithography or a combination oflithograph and etching to form openings that expose the RDL structure114.

After openings are formed in the passivation layer 116, an UBM layer 122passes through the passivation layer 116 via those openings formed inthe passivation layer 116, as shown in FIG. 10D. In some embodiments,the UBM layer 122 fills into the openings formed in the passivationlayer 116, so that each of the conductive structures 120 is electricallycoupled to the respective exposed RDL structure 114 under the opening inthe passivation layer 116.

As shown in FIG. 10E, a solder bump 124 is formed on the UBM layer 122,according to some embodiments. In some embodiments, a conductivestructure 120 includes the UBM layer 122 and the solder bump 124. Insome other embodiments, the conductive structure 120 includes aconductive bump structure such as a copper bump, a conductive pillarstructure, a conductive wire structure, or a conductive paste structure.In some embodiments, more than one conductive structures 120 are formed.As shown in FIG. 10E, the gap G1 between the conductive structures 120may be greater than the gap G2 between the RDL structures 106 to achievethe fan-out structure.

After the conductive structures 120 are formed, an optional protectiveinsulating layer 130 is formed to cover the exposed second surface 101 bof the semiconductor dies, as shown in FIG. 10E. The protectiveinsulating layer 130 is sometimes referred to as a DBF that is made of athermoset material, such as an epoxy resin material. In some otherembodiments, the protective insulating layer 130 is made of a materialthat is the same as the material of the protective insulating layer 110.For example, the protective insulating layer 130 is made of an epoxymolding compound (EMC), an Ajinomoto™ Build-up Film (ABF), or anacrylic-based material.

FIG. 10F is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 10E may be omitted forbrevity. In some embodiments, the semiconductor package structure 60 bis similar to the semiconductor package structure 60 a shown in FIG.10E. Compared to the semiconductor package structure 60 a, there is noprotective insulating layer 130 formed in the package structure 60 b,and hence the second surface 101 b of the semiconductor die is exposedto the environment. In some embodiments, the semiconductor packagestructure 60 b is formed by a method that is similar to the method shownin FIGS. 10A to 10E, except that the formation of the protectiveinsulating layer 130, as shown in FIG. 10E, is omitted.

FIG. 11A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 10E may be omitted forbrevity. In some embodiments, the semiconductor package structure 70 ais similar to the semiconductor package structure 60 a shown in FIG.10E. Compared to the semiconductor package structure 60 a, there is noUBM layer 122 formed in the package structure 70 a, and hence the solderbump 124 is formed directly on the passivation layer 116. In someembodiments, the semiconductor package structure 70 a is formed by amethod that is similar to the method shown in FIGS. 10A to 10E, exceptthat the formation of the UBM layer 122, as shown in FIG. 10E, isomitted.

As shown in FIG. 11A, the solder bump 124 may pass through thepassivation layer 116 via openings formed in the passivation layer 116.In some embodiments, the solder bump 124 fills into the openings formedin the passivation layer 116, so that each of the conductive structures120 is electrically coupled to the respective exposed RDL structure 114under the opening in the passivation layer 116.

FIG. 11B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 11A may be omitted forbrevity. In some embodiments, the semiconductor package structure 70 bis similar to the semiconductor package structure 70 a shown in FIG.11A. Compared to the semiconductor package structure 70 a, there is noprotective insulating layer 130 formed in the package structure 70 b,and hence the second surface 101 b of the semiconductor die is exposedto the environment.

FIG. 12A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 10E may be omitted forbrevity. In some embodiments, the semiconductor package structure 80 ais similar to the semiconductor package structure 60 a shown in FIG.10E. Compared to the semiconductor package structure 60 a, there is nopassivation layer 105 formed in the package structure 80 b, and hencethe RDL structure 106 is formed directly on the insulating layer 104. Insome embodiments, the semiconductor package structure 80 a is formed bya method that is similar to the method shown in FIGS. 10A to 10E, exceptthat the formation of the passivation layer 105, as shown in FIG. 10A,is omitted.

FIG. 12B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 12A may be omitted forbrevity. In some embodiments, the semiconductor package structure 80 bis similar to the semiconductor package structure 80 a shown in FIG.12A. Compared to the semiconductor package structure 80 a, there is noprotective insulating layer 130 formed in the package structure 80 b,and hence the second surface 101 b of the semiconductor die is exposedto the environment.

FIG. 13A is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 10E may be omitted forbrevity. In some embodiments, the semiconductor package structure 90 ais similar to the semiconductor package structure 60 a shown in FIG.10E. Compared to the semiconductor package structure 60 a, there is nopassivation layer 105 and no UBM layer 122 formed in the packagestructure 90 a, and hence the RDL structure 106 is formed directly onthe insulating layer 104 and the solder bump 124 is formed directly onthe passivation layer 116. In some embodiments, the semiconductorpackage structure 80 a is formed by a method that is similar to themethod shown in FIGS. 10A to 10E, except that the formation of thepassivation layer 105 and the UBM layer 122, is omitted.

FIG. 13B is a cross-sectional view of an exemplary semiconductor packagestructure in accordance with some embodiments. Descriptions of elementsof the embodiments hereinafter that are the same as or similar to thosepreviously described with reference to FIG. 13A may be omitted forbrevity. In some embodiments, the semiconductor package structure 90 bis similar to the semiconductor package structure 90 a shown in FIG.13A. Compared to the semiconductor package structure 90 a, there is noprotective insulating layer 130 formed in the package structure 90 b,and hence the second surface 101 b of the semiconductor die is exposedto the environment.

According to the foregoing embodiments, the semiconductor packagestructure is designed to fabricate a protective structure in thesemiconductor package structure to cover or encapsulate thesemiconductor die in the semiconductor package structure. The protectivestructure includes one or more protective insulating layers to protectthe semiconductor die from the environment, thereby preventing thesemiconductor die in the semiconductor package structure from damage dueto, for example, the stress, the chemicals and/or the moisture.

Due to the topside protection of semiconductor die, the reliability ofthe semiconductor package structure can be maintained during thesubsequent thermal process (such as a surface mount technology (SMT)process or a bonding process). Moreover, the RDL structure formed on thesemiconductor die is also protected by the protective structure, so asto keep its electrical and thermal performance. In addition, due to thesidewall protection of semiconductor die, the semiconductor die in thesemiconductor package structure can be prevented from chipping when theCSP structure is placed in a test socket for performing a test process.

Furthermore, the protective insulating layer covers the RDL structureand the passivation layer, the second surface and the third surface ofthe semiconductor die can provide a better protection ability of thesemiconductor package structure, according to some embodiments. Inaddition, the semiconductor die shift for the RDL structure alignmentcan be reduced or avoided. Therefore, reliability of the semiconductorpackage structure can be improved.

While the invention has been described by way of example and in terms ofthe preferred embodiments, it should be understood that the invention isnot limited to the disclosed embodiments. On the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

What is claimed is:
 1. A semiconductor package structure, comprising: asemiconductor die having a first surface, a second surface opposite thefirst surface, and a third surface adjoined between the first surfaceand the second surface; a redistribution layer (RDL) structure on thefirst surface of the semiconductor die and electrically coupled to thesemiconductor die; a protective insulating layer covering the RDLstructure, the second surface and the third surface of the semiconductordie; and a conductive structure passing through the protectiveinsulating layer and electrically coupled to the RDL structure.
 2. Thesemiconductor package structure as claimed in claim 1, furthercomprising a passivation layer between the RDL structure and theprotective insulating layer and covered by the protective insulatinglayer, wherein the conductive structure passes through the passivationlayer.
 3. The semiconductor package structure as claimed in claim 1,further comprising a passivation layer between the first surface of thesemiconductor die and the RDL structure, wherein the RDL structurepasses through the passivation layer.
 4. The semiconductor packagestructure as claimed in claim 1, further comprising: a first passivationlayer between the first surface of the semiconductor die and the RDLstructure, wherein the RDL structure passes through the firstpassivation layer; and a second passivation layer between the RDLstructure and the protective insulating layer and covered by theprotective insulating layer, wherein the conductive structure passesthrough the second passivation layer.
 5. The semiconductor packagestructure as claimed in claim 4, wherein the first passivation layercomprises a material that is the same as a material of the secondpassivation layer and different from a material of the protectiveinsulating layer.
 6. The semiconductor package structure as claimed inclaim 4, wherein the first passivation layer and the second passivationlayer respectively comprise polyimide or polybenzoxazole (PBO).
 7. Thesemiconductor package structure as claimed in claim 1, wherein theprotective insulating layer comprises an epoxy molding compound (EMC),an Ajinomoto™ Build-up Film (ABF), or an acrylic-based material.
 8. Thesemiconductor package structure as claimed in claim 1, wherein theconductive structure comprises an under-bump metallurgy (UBM) layer anda solder bump on the UBM layer, or a solder bump on the firstpassivation layer.
 9. A semiconductor package structure, comprising: asemiconductor die having a first surface, a second surface opposite thefirst surface, and a third surface adjoined between the first surfaceand the second surface; a first protective insulating layer covering thefirst surface and the third surface of the semiconductor die; a firstredistribution layer (RDL) structure over the first surface of thesemiconductor die and electrically coupled to the semiconductor die andextending to directly above the first protective insulating layer; afirst passivation layer covering the first protective insulating layerand the first RDL structure; and a plurality of conductive structurespassing through the first passivation layer and electrically coupled tothe first RDL structure.
 10. The semiconductor package structure asclaimed in claim 9, further comprising a second RDL structure betweenthe first RDL structure and the first surface of the semiconductor dieand electrically coupled to the semiconductor die.
 11. The semiconductorpackage structure as claimed in claim 10, wherein the second RDLstructure is surrounded by the first protective insulating layer on thefirst surface of the semiconductor die.
 12. The semiconductor packagestructure as claimed in claim 10, wherein the first RDL structure iselectrically coupled to the semiconductor die through the second RDLstructure.
 13. The semiconductor package structure as claimed in claim10, further comprising a second passivation layer between the second RDLstructure and the first surface of the semiconductor die, wherein thesecond RDL structure passes through the second passivation layer. 14.The semiconductor package structure as claimed in claim 13, wherein thesecond passivation layer is surrounded by the first protectiveinsulating layer on the first surface of the semiconductor die.
 15. Thesemiconductor package structure as claimed in claim 13, wherein thesecond passivation layer comprises a material that is the same as amaterial of the first passivation layer and different from a material ofthe first protective insulating layer.
 16. The semiconductor packagestructure as claimed in claim 9, further comprising a second passivationlayer between the first RDL structure and the first protectiveinsulating layer, wherein the first RDL structure passes through thesecond passivation layer.
 17. The semiconductor package structure asclaimed in claim 16, wherein the second passivation layer comprises amaterial that is the same as a material of the first passivation layerand different from a material of the first protective insulating layer.18. The semiconductor package structure as claimed in claim 9, furthercomprising a second protective insulating layer covering the secondsurface of the semiconductor die.
 19. The semiconductor packagestructure as claimed in claim 18, wherein the first protectiveinsulating layer and the second protective insulating layer comprise thesame material.
 20. The semiconductor package structure as claimed inclaim 18, wherein the first protective insulating layer and the secondprotective insulating layer respectively comprise an epoxy moldingcompound (EMC), an Ajinomoto™ Build-up Film (ABF), or an acrylic-basedmaterial.
 21. The semiconductor package structure as claimed in claim 9,wherein the conductive structure comprises an under-bump metallurgy(UBM) layer and a solder bump on the UBM layer, or a solder bump on thefirst passivation layer.
 22. A semiconductor package structure,comprising: a semiconductor die having a first surface, a second surfaceopposite the first surface, and a third surface adjoined between thefirst surface and the second surface; a first redistribution layer (RDL)structure on the first surface of the semiconductor die and electricallycoupled to the semiconductor die; a first protective insulating layercovering the first surface and the third surface of the semiconductordie and surrounding the first RDL structure; a first passivation layercovering the first protective insulating layer and the first RDLstructure; a second RDL structure electrically coupled to thesemiconductor die through the first RDL structure, wherein the secondRDL structure extends from the first RDL structure to above the firstprotective insulating layer; a second passivation layer covering thesecond RDL structure; and a plurality of conductive structures passingthrough the second passivation layer and electrically coupled to thesecond RDL structure.
 23. The semiconductor package structure as claimedin claim 22, further comprising a second protective insulating layercovering the second surface of the semiconductor die.
 24. Thesemiconductor package structure as claimed in claim 22, furthercomprising a third passivation layer between the first surface of thesemiconductor die and the first RDL structure, wherein the first RDLstructure passes through the third passivation layer.
 25. Thesemiconductor package structure as claimed in claim 24, wherein thethird passivation layer is surrounded and covered by the firstprotective insulating layer.
 26. The semiconductor package structure asclaimed in claim 24, wherein the first passivation layer, the secondpassivation layer and the third passivation layer comprise a materialthat is different from a material of the first protective insulatinglayer.
 27. The semiconductor package structure as claimed in claim 24,wherein the first passivation layer, the second passivation layer andthe third passivation layer respectively comprise polyimide orpolybenzoxazole (PBO).
 28. The semiconductor package structure asclaimed in claim 22, wherein the conductive structure comprises anunder-bump metallurgy (UBM) layer and a solder bump on the UBM layer, ora solder bump on the second passivation layer.